The present disclosure relates to variable gain amplifiers (VGAs), and more particularly to low distortion VGAs having wide variable-gain ranges suitable for wireless communication devices.
With the advancement of CMOS process technologies in recent years, the performance of MOS transistors has improved dramatically. Thus, it is becoming possible to implement a receiver of a wireless communication device, which conventionally uses SiGe bipolar transistors etc. having superior high-frequency characteristics, using MOS transistors. Implementing a receiver using CMOS transistors allows the receiver and a digital demodulator using CMOS transistors to be integrated on one chip, thereby allowing cost reduction, size reduction, and reduction in power consumption of a wireless communication device. Accordingly, technology for implementing receivers using CMOS transistors has been actively studied in development of various wireless communication devices.
However, although technology for implementing television tuners, which are particularly in high demand among wireless communication devices, using CMOS transistors has been studied for years, such studies have not significantly advanced. The reason is that the television broadcast signals are broadband signals and include multiple channels, and that requirements for a high sensitivity characteristic and a high interferer-resistance characteristic make it difficult for a CMOS process using only a low supply voltage to satisfy the specifications. For example, in a television tuner for the digital terrestrial television broadcasting in Japan (Integrated Services Digital Broadcasting-Terrestrial (ISDB-T)), an input signal has a signal frequency band of 6 MHz per channel, and includes 50 channels ranging from channel 13 (473.143 MHz) to channel 62 (767.143 MHz). In addition, each reception channel is required to have a sensitivity characteristic of about −84 dBm, and at the same time, to have an interferer-resistance characteristic from 45 dBc to 60 dBc at the input level of an interference channel of −8 dBm.
In order to achieve such reception characteristics, design of a VGA (low noise amplifier) which processes a signal immediately after being received by an antenna is particularly important. That is, it would be possible to say that successful implementation of a desired tuner depends on how well a wide variable-gain range and a low distortion characteristic are achieved at a lower gain setting, while retaining a predetermined noise characteristic. However, it is very difficult that a CMOS process, in which only a low supply voltage can be used, satisfies the specification, in particular, on distortion among the required specifications.
To illustrate this in detail, a distortion characteristic of a general CMOS amplifier will be described below. FIG. 16 illustrates a circuit configuration of a general source-grounded amplifier. A signal Vin is input through a direct current (DC) blocking capacitor 1 to the gate terminal of an amplifier transistor 41, which is biased using a bias voltage generator 100 and a bias resistor 2, and then is converted into a current signal. After this, the current signal is converted into a voltage signal Vout by a load impedance unit 3.
In general, it is known that the distortion characteristic of an amplifier is improved by increasing the bias voltage supplied from the bias voltage generator 100. This will be quantitatively explained below using mathematical formulae.
Let x be the input, and let y be the output in the amplifier of FIG. 16. Then, using an approximation by a nonlinear cubic polynomial, the input versus output characteristic can be expressed by the following equation.y=α1·x+α2·x2+α3·x3  (1)
An index of the distortion characteristic IIP3 can be expressed by the following equation (see, e.g., Kunihiko Iizuka, Document of Invited Lecture at IEICE17th Technical Meeting on Silicon Analog RF Technologies “Trend toward Integration of RF Circuits for Television Broadcast Receivers,” Sep. 29, 2008, p. 31 (Non-Patent Document 1)). Here, gm represents the transconductance of the amplifier transistor 41, and gm″ represents the second-order derivative of gm.
                              IIP          ⁢                                          ⁢          3                =                                                            4                3                            |                                                α                  ⁢                                                                          ⁢                  1                                                  α                  ⁢                                                                          ⁢                  3                                            |                                ≈                                    8              ⁢                              gm                                  gm                  ″                                                                                        (        2        )            
Meanwhile, it is known that a drain current Ids of a MOS transistor, taking into account the velocity saturation of carrier, is given by the following equation. Here, μ0 is the mobility, COX is the capacitance of the oxide layers, W is the channel width, L is the channel length, Vgs is the gate-to-source voltage, Vth is the threshold voltage, and ξ is a coefficient. For simplicity of the equation, a variable Veff(=Vgs−Vth) is used.
                                                        Ids              =                                                                                          μ                      0                                        ·                                          C                      ox                                                        2                                ⁢                                  (                                      W                    L                                    )                                ⁢                                                                            (                                                                        V                          gs                                                -                                                  V                          th                                                                    )                                        2                                                        1                    +                                          ξ                      ·                                              (                                                                              V                            gs                                                    -                                                      V                            th                                                                          )                                                                                                                                                                    =                                                                                          μ                      0                                        ·                                          C                      ox                                                        2                                ⁢                                  (                                      W                    L                                    )                                ⁢                                                      V                    eff                    2                                                        1                    +                                          ξ                      ·                                              V                        eff                                                                                                                                                    (        3        )            
The variables gm and gm″ are respectively obtained by differentiating Ids once and three times with respect to Veff, and can be expressed by the following equations.
                    gm        =                                                            ⅆ                I                            ⁢                              ⅆ                s                                                    ⅆ                              V                eff                                              =                                                                      μ                  0                                ·                                  C                  ox                                            2                        ⁢                          (                              W                L                            )                        ⁢                                                            2                  ·                                      V                    eff                                                  +                                  ξ                  ·                                      V                    eff                    2                                                                                                (                                      1                    +                                          ξ                      ·                                              V                        eff                                                                              )                                2                                                                        (        4        )                                          gm          ″                =                                                                              ⅆ                  3                                ⁢                I                            ⁢                              ⅆ                s                                                    ⅆ                              V                eff                3                                              =                                                    -                3                            ·              ξ              ·                              μ                0                            ·                                                C                  ox                                ⁡                                  (                                      W                    L                                    )                                                      ⁢                          1                                                (                                      1                    +                                          ξ                      ·                                              V                        eff                                                                              )                                4                                                                        (        5        )            
Substituting Equations 4 and 5 into Equation 2, the index IIP3 can be expressed by the following equation.
                              IIP          ⁢                                          ⁢          3                =                                            4              ⁢                                                V                  eff                                ·                                  (                                      2                    +                                          ξ                      ·                                              V                        eff                                                                              )                                            ⁢                                                (                                      1                    +                                          ξ                      ·                                              V                        eff                                                                              )                                2                                                    3              ⁢                                                          ⁢              ξ                                                          (        6        )            
Equation 6 means that an increase in Veff improves the distortion characteristic. That is, in the amplifier of FIG. 16, an increase in the bias voltage supplied from the bias voltage generator 100 allows the distortion characteristic to be improved (see FIG. 17).
However, improvement of IIP3 by increasing Veff has a limit. An excessively high Veff will prevent the amplifier transistor 41 from operating in a saturation region due to a limit of the supply voltage, thereby significantly deteriorate the function as an amplifier, including the distortion characteristic. That is, there is an optimum value for Veff to maximize IIP3, and the optimum value decreases as the supply voltage decreases. Accordingly, achieving a low distortion characteristic with a low supply voltage is very difficult.
Next, a description of a VGA will be presented. FIG. 18 illustrates a circuit configuration of a general VGA. A variable bias voltage generator 101 adjusts the bias voltage supplied to the amplifier transistor 41 based on the control of a gain controller 102, thereby allowing a variable gain to be achieved.
However, a decrease in the bias voltage when a low gain has been set causes the distortion characteristic to significantly deteriorate (see FIG. 17). In order to avoid this, VGAs have been used in recent years, which are each capable of controlling the gain without decreasing the bias voltage by controlling the effective size of the amplifier transistor utilizing the switching characteristic of MOS transistors. For example, some devices achieve variable gains by each providing a variable amplifier unit having a variable transistor size in place of the amplifier transistor 41, and by changing the transistor size of the variable amplifier unit while keeping the bias voltage constant (see, e.g., U.S. Pat. No. 6,657,498 (FIG. 3(a)) (Patent Document 1)).